The present invention generally concerns a differential sense amplifier used in a semiconductor memory device. In particular, this invention relates to a sense amplifier which may have stable, good amplification characteristics, without causing great power cosumption.
A semiconductor memory device requires, in order to read out the data stored in its memory cells, a circuit for decoding addresses to select a series of memory cells, an amplifier for amplifying the data read out from the selected memory cells, and a circuit outputting the amplified data. Generally, when fabricating a highly integrated semiconductor memory device with high speed performance, the improvement of its reliability as well as the least power cosumption must be primarily considered.
Particularly, as the semiconductor memory device gets more highly integrated, both of the operating voltage level of the memory device and the voltage difference between the data lines get reduced, so that there is required a sense amplifier to surely sense the reduced voltage difference. The amplifiers used mainly in a semiconductor memory device, particularly a static random access memory (SRAM), are differential sense amplifiers, which are to amplify the small voltage difference between both input terminals of a pair of data lines (bit lines).
Such a sense amplifier is generally of a current mirror type, whose fundamental structure is disclosed in U. S. Pat. No. 4,697,112 and the article entitled "A 28ns CMOS SRAM With Bipolar Sense Amplifiers", PP 224-225, IEEE ISSCC published on Feb. 23, 1984.
Referring to FIG. 1 for illustrating a conventional circuit including the sense amplifier disclosed in the above publications, the circut amplifies the difference between the voltages applied to first and second input terminals 1 and 2, which are output through a first and second output terminals 3 and 4. Since there is no substantial voltage difference between the gate and drain of a p-channel metal oxide semiconductor (PMOS) transistor 6 that are commonly connected with each other, the voltage of the first output terminal 3 does not suffer a considerable change in spite of variation of the input signal level.
Thus, the effective output is obtained through only the second output terminal 4, and therefore the circuit is called a single ended type. Hence, a practical memory device uses two single ended current mirror type sense amplifiers, as shown in FIG. 2.
In FIGS. 1 and 2, an N-type metal oxide semiconductor (NMOS) transistor 11 with the source coupled to the ground voltage Vss is to prevent power consumption in respomse to a sense amplifier control signal 10 of the logic "low" state received by its gate when sense amplifier is not operated.
The equalization signal 12 applied to an equalization transmission gate 13 connected between a pair of bit lines (or data lines) 15 and 16 equalizes the bit lines 15 and 16 before and after the operation of the sense amplifier, while becoming the logic "high" so as to cause the output signal of the sense amplifier to appear in the bit lines (or data lines) during the operation thereof.
Using the above current mirror type sense amplifier involves the following problems.
First, if the voltage level of the input signals is relatively low or high, the gain of out put voltage becomes small. The reason is that although no problem would be caused if there would be formed a voltage difference between the input voltages including the threshold voltages of the NMOS transistors 8 and 9 (See FIG. 1) receiving the input voltages, however the voltage difference between the first and second output terminals 3 and 4 becomes insignificant because the NMOS transistors have almost same conductivity if the levels of the two inputs are different below or over the threshold voltage.
Second, the operation speed is very low. The reason is that if the signal received through the first input terminal 1 has a higher level than the signal received through the second input terminal 2, the NMOS transistor 8 gets into the conductive state faster compared with the normal state, thereby lowering the voltage of the first output terminal 3. Consequently, the PMOS transistor 7 charges the second output terminal 4 with the power supply voltage Vcc, so that the variation of output voltages is caused. The time taken for the variation depends on the conductivity of the transistor itself, so that the effective output appears relatively slow.
In order to improve the current mirror type sense amplifier, there has been proposed another conventional sense amplifier as shown in FIG. 3.
The latch type sense amplifier as shown in FIG. 3 has a first and second output terminals 53 and 54 cross-coupled respectively to the gates of PMOS transistors 57 and 56.
This structure is to compensate for the insufficient positive feedback effect of the first states prior art that is caused by the PMOS transistors 6, 7 coupled to the power supply in the circuit of FIGS. 1 and 2 working in the saturation region. However, the sense amplifier of FIG. 3 also shows dropping of the output voltage gain at a low or high level of the input signal.
Namely, referring to the graph of FIG. 6, it will be readily appreciated that the voltage gain curves 61 and 63 respectively representing the voltage gain characteristics of the circuits of FIGS. 2 and 3 rapidly drop when the level of the input voltage is below 2 V or over 3 V. The reason is that because the parts for receiving the input voltages in the circuits of FIGS. 2 and 3 are NMOS transitors, the voltage level region (or bandwidth) for maintaining high output voltage gain as described above is narrow.
Moreover, in the conventional circuits of FIGS. 1 or 3, if the sense amplifier control signal 10 is caused to become the logic "low" in order to prevent power consumption when the sense amplifier is not operated, the NMOS transistor 11 is turned off thereby disconnecting the currents flowing through the NMOS transistors 8, 9 or 58, 59 and the voltages of the first and second output terminals 3, 4 or 53, 54 rise until the PMOS transistors 6, 7 or 56, 57 are turned off.
Thus, the voltage levels of both output terminals come to have the same value, so that the loss of the originally effective output signal of the sense amplifier will be caused. In order to solve this problem, a lacth circuit may be additionally added between the first and second output terminals 3, 4 or 53, 54.